1. Field of the Invention
The present invention relates to the field of adapting a received input data stream at one clock rate to another clock rate. In particular, the present invention is related to using a buffer to write data in at one clock rate and read data out at another clock rate, while compensating for the rate variations using idles.
2. Background
In high-speed data communications, transitions can occur between clocks as data is conveyed across different channels. These transitions can cause clocking errors or data errors if the transitions are not compensated for. One such transition occurs in 10 Gb (Gigabit) Ethernet in the transition from the domain of the XGXS clock to that of the PMA clock. The required clock rates are the same, 156.25 MHz. However, the clocks are required to be accurate only to within +/−100 ppm. As a result, the clocks may differ in total by as much as +/−200 ppm. At the high data rates of 10 Gb Ethernet this difference can be very significant. The Ethernet standards set forth the clock rates, clock accuracy standards, bit rates, and data packet formats. The Ethernet standards also set forth that idles can be used to compensate for clock rate and other discrepancies and the permissible locations and structures for any idles that are used in a packet. However, there is no standard on how to insert and delete idles in order to accommodate such transitions between disparate clock domains.